#include "unity.h"
#include "mock_bsp_test_commom.h" // CMock 生成的 mock 头文件
#include "Rt_ModeCode_intr_config.h"

// 测试实例
XRt1553B testInstance;

void setUp(void)
{
    // 初始化结构体
    memset(&testInstance, 0, sizeof(XRt1553B));
    testInstance.BaseAddress = 0x1000;
}

void tearDown(void)
{
    // 清理
}

// TC001: 所有中断关闭
void test_Rt_ModeCode_intr_config_all_disabled(void)
{
    // 所有配置为 DISABLE
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // 预期所有寄存器写入 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // 不会读取或设置任何位
    rt_ModeCode_intr_config(&testInstance);
}

// TC002: 所有中断开启
void test_Rt_ModeCode_intr_config_all_enabled(void)
{
    // 所有配置为 ENABLE
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_ENABLE, sizeof(testInstance.ModeCode_cfg));

    // 初始化寄存器为 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // 设置前 9 个发送中断
    u32 i = 0;
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));

    // 设置其他中断
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 1 << XRT53_MODECODE_INTR_LOC_TRANS_VECTOR);

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 1 << XRT53_MODECODE_INTR_LOC_SYNC_WITH_DATA);

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 1 << XRT53_MODECODE_INTR_LOC_TRANS_LASR_CMD);

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 1 << XRT53_MODECODE_INTR_LOC_TRANS_BIT_WORD);

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 1 << XRT53_MODECODE_INTR_LOC_SEL_TX_SHUTDOWN_ENABLE);

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, (1 << XRT53_MODECODE_INTR_LOC_SEL_TX_SHUTDOWN_DISABLE));

    rt_ModeCode_intr_config(&testInstance);
}

// TC003: Partial send mode commands enabled (first 3)
void test_Rt_ModeCode_intr_config_partial_send_modes(void)
{
    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // 设置前 3 个发送中断
    testInstance.ModeCode_cfg.DynamicBusControl_IntrEnable = XRT53_MODECODE_INTR_ENABLE;
    testInstance.ModeCode_cfg.Sync_IntrEnable = XRT53_MODECODE_INTR_ENABLE;
    testInstance.ModeCode_cfg.TransStatWord_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // 初始化寄存器为 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // 前3中断判定
    u32 i = 0;
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, (1 << i++));

    rt_ModeCode_intr_config(&testInstance);
}

// TC004: Transmit vector word enabled
void test_Rt_ModeCode_intr_config_transmit_vector_enabled(void)
{

    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable transmit vector word interrupt
    testInstance.ModeCode_cfg.TransVector_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // 初始化寄存器为 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // for 循环不执行

    // 执行if 矢量字
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 1);


    rt_ModeCode_intr_config(&testInstance);
}

// TC005: Sync with data enabled
void test_Rt_ModeCode_intr_config_sync_with_data_enabled(void)
{
    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable sync with data interrupt
    testInstance.ModeCode_cfg.SyncwithData_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // Expect initial register writes to 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // Expect read and write for RX_MSB with sync with data bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_SYNC_WITH_DATA);

    rt_ModeCode_intr_config(&testInstance);
}

// TC006: Transmit last command enabled
void test_Rt_ModeCode_intr_config_transmit_last_command_enabled(void)
{
    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable transmit last command interrupt
    testInstance.ModeCode_cfg.TransLastCommand_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // Expect initial register writes to 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // Expect read and write for TX_MSB with transmit last command bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_TRANS_LASR_CMD);

    rt_ModeCode_intr_config(&testInstance);
}

// TC007: Transmit BIT enabled
void test_Rt_ModeCode_intr_config_transmit_bit_enabled(void)
{
    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable transmit BIT interrupt
    testInstance.ModeCode_cfg.TransBIT_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // Expect initial register writes to 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // Expect read and write for TX_MSB with transmit BIT bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_TRANS_BIT_WORD);

    rt_ModeCode_intr_config(&testInstance);
}

// TC008: Selected transmitter shutdown enabled
void test_Rt_ModeCode_intr_config_selected_transmitter_shutdown_enabled(void)
{
    // Enable selected transmitter shutdown interrupt
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable transmit BIT interrupt
    // testInstance.ModeCode_cfg.TransBIT_IntrEnable = XRT53_MODECODE_INTR_ENABLE;
    testInstance.ModeCode_cfg.SelTransmitterShutdown_IntrEnable = XRT53_MODECODE_INTR_ENABLE;

    // Expect initial register writes to 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // Expect read and write for TX_MSB with transmit BIT bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_SEL_TX_SHUTDOWN_ENABLE);

    rt_ModeCode_intr_config(&testInstance);


}

// TC009: Combination test - multiple interrupts enabled
void test_Rt_ModeCode_intr_config_combination_enabled(void)
{
    // Initialize all to disabled
    memset(&testInstance.ModeCode_cfg, XRT53_MODECODE_INTR_DISABLE, sizeof(testInstance.ModeCode_cfg));

    // Enable a combination of interrupts
    testInstance.ModeCode_cfg.DynamicBusControl_IntrEnable = XRT53_MODECODE_INTR_ENABLE;           // Bit 0
    testInstance.ModeCode_cfg.OverrideTransmitterShutdown_IntrEnable = XRT53_MODECODE_INTR_ENABLE; // Bit 5
    testInstance.ModeCode_cfg.TransVector_IntrEnable = XRT53_MODECODE_INTR_ENABLE;                 // TX_MSB bit 0
    testInstance.ModeCode_cfg.SyncwithData_IntrEnable = XRT53_MODECODE_INTR_ENABLE;                // RX_MSB bit 4

    // Expect initial register writes to 0
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTTX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_BCSTRX_MSB_OFFSET, 0);

    // Expect read and write for TX_LSB with bits 0 and 5 set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 1); // bits 0

    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_LSB_OFFSET, 1<<5); // bits  5

    // Expect read and write for TX_MSB with transmit vector bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_TX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_TRANS_VECTOR);

    // Expect read and write for RX_MSB with sync with data bit set
    XRt1553B_ReadMem_ExpectAndReturn(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET, 0);
    XRt1553B_WriteMem_Expect(testInstance.BaseAddress, XRT53_MODECODE_INTR_RX_MSB_OFFSET,
                             1 << XRT53_MODECODE_INTR_LOC_SYNC_WITH_DATA);

    rt_ModeCode_intr_config(&testInstance);
}